1. Field of the Invention
The present invention relates to a switching control circuit and a self-excited DC-DC converter.
2. Description of the Related Art
A DC-DC converter is a local switching power source built into an electronic device and is classified broadly into an externally excited type and a self-excited type. The DC-DC converter has at least one switching element that chops a direct-current input voltage Vin and control ON/OFF of the switching element to chop the input voltage Vin. In this switching power source, the chopped input voltage Vin is smoothed by a LC smoothing circuit, etc., to acquire an output voltage Vout at a certain target level that is different from the level of the input voltage Vin. With such an arrangement, the DC-DC converter can supply a power supply voltage necessary for a load side circuit connected to the DC-DC converter.
FIG. 6 shows the configuration of a conventional externally excited DC-DC converter 300.
The externally excited DC-DC converter 300 is provided with NMOS transistors Q1, Q2 serially connected between a power supply line of an input voltage Vin and a ground line, and the NMOS transistors Q1, Q2 are turned on/off by a drive circuit 40 in a complementary manner. As a result, a rectangular-wave signal indicating H-level or L-level appears at the connecting point of the NMOS transistors Q1, Q2 and is supplied to a LC smoothing circuit constituted by a smoothing coil L and a capacitance element C1. In this way, an output voltage Vout is generated, which has been stepped down compared to the input voltage Vin and smoothed.
The output voltage Vout is divided by resistance elements R1, R2 for adjusting the target level to produce a voltage (=R2/(R1+R2)), which is returned to an error amplifier 100. The error amplifier 100 integrates and outputs an error between a divided voltage Vf which varies depending on the output voltage Vout and a reference voltage Vref. A PWM comparator 120 compares a triangular wave voltage output by a triangular wave oscillator 110 and the output of the error amplifier 100 to generate a PWM (Pulse Width Modulation) signal P that turns on/off the NMOS transistors Q1, Q2 via the drive circuit 40. In this case, the NMOS transistor Q1 is on during a period when the PWM signal P is at H-level (NMOS transistor Q2 is off) and is off during a period when the PWM signal P is at L-level (NMOS transistor Q2 is on).
It is assumed that the output voltage Vout of the externally excited DC-DC converter 300 becomes higher than a steady level because of disturbance or the like. In this case, since the divided voltage Vf follows the output voltage Vout and becomes higher, the error voltage (Vref−Vf) output from the error amplifier 100 is gradually reduced. As a result, an H-level pulse width is shortened in the PWM signal P output from the PWM comparator 120. Since the ON period of the NMOS transistor Q1 is shortened, the level of the output voltage Vout is lowered and the output voltage Vout is controlled in the direction of returning to the steady state. On the other hand, if the output voltage Vout becomes a level lower than the reference voltage Vref, although in an operation opposite to the above, the output voltage Vout is controlled in the direction of returning to the steady state likewise.
By the way, it is known that it is difficult to speed up the operation of the separately excited DC-DC converter 300 because the divided voltage Vf must go through the error amplifier 100 before the divided voltage Vf is used in the PWM comparator 120. Specifically, the error amplifier 100 with the resistance element R1 and the capacitance element Cr constitutes an integral circuit. Therefore, if the output voltage Vout rapidly changes, the error amplifier 100 cannot quickly output the output result corresponding to the rapid change. Therefore, the error amplifier 100 takes time to perform controls corresponding to the rapid change in the output voltage Vout.
Accordingly, a proposal has been made of a self-excited DC-DC converter having removed therefrom the error amplifier 100, which is an inhibiting factor of the fast control response, and the triangular wave oscillator 110. Since the fluctuations (i.e., ripple) of the output voltage Vout directly appear as changes in the ON/OFF periods of the switching element, the self-excited DC-DC converter has faster control responsiveness and is suitable for a power supply application that requires faster responsiveness to load fluctuations. This type of the self-excited DC-DC converter is generally referred to as “ripple converter” (see, e.g., Japanese Patent Application Laid-Open Publication No. 2005-110369).
FIG. 7 shows a typical configuration of a conventional ripple converter 310 (hereinafter, “ripple converter 310 of a first conventional example”). A difference from the externally excited DC-DC converter 300 shown in FIG. 6 is that a ripple comparator 10 and a delay circuit 30 are disposed instead of the error amplifier 100, the triangular wave oscillator 110, and the PWM comparator 120. The same reference numerals indicate the same components as in FIG. 6, which will not be described.
The ripple comparator 10 is embodied as a so-called differential comparator that has an inverting input terminal for applying a divided voltage Vf obtained by dividing a ripple-like output voltage Vout to, an non-inverting input terminal for applying a reference voltage Vref to be compared with the divided voltage Vf and corresponding to the target level of the output voltage Vout to, and an output terminal for outputting a switching control signal D that turns on/off the NMOS transistors Q1, Q2 via the drive circuit 40 depending on the level comparison result between the divided voltage Vf and the reference voltage Vref. With regard to a switching control signal D′ generated by delaying the switching control signal D by the delay circuit 30, the NMOS transistor Q1 is on during the H-level period and the NMOS transistor Q2 is on during the L-level period.
The delay circuit 30 delays the switching control signal D by a predetermined delay time Td before the switching control signal D output from the ripple comparator 10 is supplied to the NMOS transistors Q1, Q2. Therefore, since the ON/OFF periods of the NMOS transistor Q1, Q2 change following the change in the delay time Td, it can be said that the delay circuit 30 is for setting the switching frequencies of the NMOS transistors Q1, Q2 to desired values. By the way, other than the delay time Td of the delay circuit 30, the ripple comparator 10 and the drive circuit 40 have delays and the NMOS transistors Q1, Q2 have switching delays. However, these delays are ignored in the following description based on the premise that these delays are extremely shorter than the delay time Td of the delay circuit 30.
FIG. 8 shows waveform diagrams of major signals of the ripple converter 310 of the first conventional example in the case of a step-down ratio of “½”. The “step-down ratio of ½” is the case that the input voltage Vin of 10V is stepped down to the output voltage of 5V, for example, and each on-duty of the NMOS transistors Q1, Q2 is “½” in this case.
The ripple comparator 10 outputs the H-level switching control signal D when the divided voltage Vf does not exceed the reference voltage Vref and outputs the L-level switching control signal D when the divided voltage Vf exceeds the reference voltage Vref (see FIG. 8 (a), (b)). The switching control signal D′ delayed by the delay time Td is generated when the switching control signal D goes through the delay circuit 30 (see FIG. 8 (b), (c)). The switching control signal D′ is supplied to the NMOS transistors Q1, Q2.
Therefore, the NMOS transistor Q1 is not turned off (the NMOS transistor Q2 is not turned on) when the divided voltage Vf becomes higher than the reference voltage Vref, and the NMOS transistor Q1 is turned off (the NMOS transistor Q2 is turned on) when the delay time Td has elapsed after the divided voltage Vf becomes higher than the reference voltage Vref. Similarly, the NMOS transistor Q1 is turned on (the NMOS transistor Q2 is turned off) when the delay time Td has elapsed after the divided voltage Vf becomes lower than the reference voltage Vref (see FIG. 8 (a), (d), (e)). As a result, the waveform of the divided voltage Vf is in the form of a triangular wave having the same slope of rising and falling with the on-duty of “½”, and the average level (direct-current component) of the divided voltage Vr coincides with the reference voltage.
It is assumed that the output voltage Vout of the ripple converter 310 of the first conventional example becomes higher than a steady state because of disturbance or the like. In this case, since the divided voltage Vf becomes higher following the output voltage Vout, an H-level pulse width is shortened in the switching control signal D output from the ripple comparator 10. As a result, since the ON period of the NMOS transistor Q1 is shortened, the level of the output voltage Vout is lowered and the output voltage Vout is controlled in the direction of returning to the steady state. On the other hand, if the output voltage Vout becomes a level lower than the reference voltage Vref, although in an operation opposite to the above, the output voltage Vout is controlled in the direction of returning to the steady state likewise.
In the ripple converter 310 of the first conventional example, the following disadvantages are pointed out. FIG. 9 shows waveform diagrams of major signals of the ripple converter 310 of the first conventional example when the step-down ratio is smaller than “½”. As shown in FIG. 9 (a), if the step-down ratio is different from “½”, the triangular wave of the divided voltage Vr has different slopes of rising and falling. The delay time Td of the delay circuit 30 is fixed. Therefore, a difference is generated between the reference voltage Vref applied to the ripple comparator 10 and the average level of the divided voltage Vf.
Describing specifically with numeric values, for example, for the ripple converter 310 of the first conventional example as shown in FIG. 7, the following are assumed: the variable range of the input voltage Vin is 7.5 V to 20 V; the target level of the output voltage Vout is 5 V; the resistance element R1 is 4 kΩ; the resistance element R2 is 1 kΩ; and the reference voltage Vref is 1 V.
When the input voltage Vin is 10 V, the divided voltage Vf shows a waveform with an on-duty of ½ (see FIG. 8 (a)) because the step-down ratio=½, and the average level of the divided voltage Vf coincides with 1 V of the reference voltage Vref. Therefore, the output voltage Vout remains at 5 V.
On the other hand, when the input voltage Vin is 15 V, the divided voltage Vf has a narrower on-duty (see FIG. 9 (a)) because the step step-down ratio=⅓, and the average level of the divided voltage Vf is somewhat higher than 1 V of the reference voltage Vref. For example, if the average level of the divided voltage Vf is 1.02 V, the output voltage Vout is 5.1V (=1.02 V×(4 kΩ+1 kΩ)/1 kΩ), and the output voltage Vout changes by 2.
When the input voltage Vin is 7.5 V, the divided voltage Vf has a wider on-duty (inverse state of FIG. 9 (a)) because the step step-down ratio=⅔, and the average level of the divided voltage Vf is somewhat lower than 1 V of the reference voltage Vref. For example, if the average level of the divided voltage Vf is 0.98 V, the output voltage Vout is 4.9V (=0.98 V×(4 kΩ+1 kΩ)/1 kΩ), and the output voltage Vout changes by 2.
In this way, the ripple converter 310 of the first conventional example has a deviation between the reference voltage Vref and the average level of the divided voltage Vf, and this deviation causes the problem that when the input voltage Vin changes, the output voltage Vout changes, which is supposed to be constant. To solve the problem due to the deviation, another ripple converter 320 (hereinafter, “ripple converter 320 of a second conventional example”) is proposed where an output correction circuit 60 shown in FIG. 10 has been introduced to the ripple converter 310 of the first conventional example shown in FIG. 7. The same reference numerals indicate the same components as in FIG. 7, which will not be described.
For example, the output correction circuit 60 comprises an error amplifier 61 that has an inverting input terminal for applying the divided voltage Vf to, an non-inverting input terminal for applying the reference voltage Vref to, and an output terminal for outputting an error integral voltage VE between the divided voltage Vf and the reference voltage Vref; and a capacitance element C2 connected to a signal line between the output terminal of the error amplifier 61 and the non-inverting input terminal of the ripple comparator 10.
That is, to make the average level of the divided voltage Vf match the reference voltage Vref, i.e., to eliminate the aforementioned deviation, the output correction circuit 60 amplifies a relative error of the divided voltage Vf with respect to the reference voltage Vref and outputs a current for charging and discharging the capacitance element C2 thereby generating the error integral voltage VE. The ripple comparator 10 uses the error integral voltage VE generated in the output correction circuit 60 as a comparison voltage that is a comparison target for the divided voltage Vf. As a result, the divided voltage Vf and the reference voltage Vref applied to the error amplifier 61 are imaginarily shorted and adjusted so that the average level of the divided voltage Vf coincides with the reference voltage Vref. For example, in the case of the aforementioned numeric value example, when the input voltage Vin is 15 V, the voltage applied to the non-inverting input terminal of the ripple comparator 10 is 0.98 V (=1/1.02 V), and when the input voltage Vin is 7.5 V, the voltage applied to the non-inverting input terminal of the ripple comparator 10 is 1.02 V (=1/0.98 V). In this way, the problem due to the aforementioned deviation can be solved.
By the way, regardless of whether the DC-DC converter is the externally excited type or the self-excited type, the components such as the NMOS transistors Q1, Q2 or a circuit on the load side may be damaged because its output current Iout exceeds a predetermined OCP (Over Current Protection) level for some reason. To prevent such an event, the DC-DC converter is usually provided with a mechanism for overcurrent protection (see, e.g., Japanese Patent Application Laid-Open Publication No. H07-245874).
FIG. 11 is a diagram for describing the configuration of a DC-DC converter with the overcurrent protection function.
An overcurrent state detection circuit 50 detects the output current Iout of the DC-DC converter and compares it with a predetermined threshold value used as a criterion for determining whether being in the overcurrent state or not and generates a state signal S indicating the comparison result.
If the state signal S generated by the overcurrent state detection circuit 50 indicates being in the overcurrent state, an overcurrent protection circuit 51 generates an overcurrent protection signal P to turn off the NMOS transistor Q1 (turn on the NMOS transistor Q2) through the drive circuit 40 to reduce the output current Iout and the level of the output voltage Vout. When the state signal S subsequently indicates being not in the overcurrent state, the overcurrent protection circuit 51 stops the overcurrent protecting operation (makes the overcurrent protection signal P invalid) and switches to the normal operation.
For example, if the overcurrent protection mechanism shown in FIG. 11 is simply provided in the ripple converter 310 of the first conventional example shown in FIG. 7 and the ripple converter 320 of the second conventional example shown in FIG. 10, the following problems will occur.
If the overcurrent protection mechanism is provided in the ripple converter 310 of the first conventional example, the NMOS transistor Q1 is turned off (the NMOS transistor Q2 is turned on) at OCP points where a voltage changing according to the output current Iout, i.e., an output direct-current detection voltage Vd exceeds a reference voltage VOCP corresponding to the overcurrent state, and the level of the output direct-current detection voltage Vd decreases. As a result, the output direct-current detection voltage Vd becomes lower than the reference voltage VOCP, and the overcurrent protection circuit 51 stops the overcurrent protecting operation and switches to the normal operation. Since the level of the output voltage Vout has decreased, the ripple converter 310 of the first conventional example is controlled in the direction of turning on the NMOS transistor Q1 (turning off the NMOS transistor Q2). Therefore, the output direct-current detection voltage Vd becomes higher than the reference voltage VOCP again.
In this way, as shown in FIG. 12, the ripple converter 310 of the first conventional example repeats a series of operations of causing the output direct-current detection voltage Vd to become higher than the reference voltage VOCP, turning off the NMOS transistor Q1, and causing the output direct-current detection voltage Vd to become lower than the reference voltage VOCP, at a high speed. Therefore, the switching frequencies of the NMOS transistors Q1, Q2 become very high, which increases the switching loss, and the components of the ripple converter 310 of the first conventional example may be damaged.
If the overcurrent protection arrangement is provided in the ripple converter 320 of the second conventional example, as shown in FIG. 13, when the output current Iout switches from the steady state to the overcurrent state (at time T1 of FIG. 13), the level of the output voltage Vout is reduced by the overcurrent protection mechanism (see FIG. 13 (a), (b)). Since the level of the output voltage Vout is reduced, the level of the divided voltage Vf is also reduced and thus the error between the two inputs for the error amplifier 61 is enlarged. Hence the level of the error integral voltage VE is increased (see FIG. 13 (b), (c)). That is, the level of the reference voltage Vref applied to the ripple comparator 10 is increased.
When the output current Iout returns from the overcurrent state to the steady state in such a condition (at time T2 of FIG. 13), the error integral voltage VE maintains its level higher than the steady state until the divided voltage Vf becomes approximately equal to the reference voltage Vref. Since the responsiveness at high-frequency of the output correction circuit 60 is lowered, it takes time for the level of the error integral voltage VE to decrease even after the divided voltage Vf becomes approximately equal to the reference voltage Vref (see FIG. 13 (b), (c)). Therefore, there is the problem that the overshoot of the output voltage Vout occurs after the overcurrent protection is released.